IEC 62047-37:2020 pdf free download – Semiconductor devices – Micro-electromechanical devices

02-10-2022 comment

IEC 62047-37:2020 pdf free download – Semiconductor devices – Micro-electromechanical devices
1 Scope
This part of IEC 62047 specifies test methods for evaluating the durability of MEMSpiezoelectric thin film materials under the environmental stress of temperature and humidityand under mechanical stress and strain,and test conditions for appropriate qualityassessment. Specifically,this document specifies test methods and test conditions formeasuring the durability of a DUT under temperature and humidity conditions and appliedvoltages. lt further applies to evaluations of direct piezoelectric properties in piezoelectric thinfilms formed primarily on silicon substrates, i.e. piezoelectric thin films used as acousticsensors, or as cantilever-type sensors.
This document does not cover reliability assessments,such as methods of predicting thelifetime of a piezoelectric thin film based on a Weibull distribution.
4.2Initial measurements
The methods of measurement used in the environmental tests shall conform to the methodsdescribed in IEC 62047-30. The ambient conditions for measurements shall include anambient temperature of 25 °C± 3°C, a relative humidity of 45 % to 75 %,and an atmosphericpressure of 86 kPa to 106 kPa.
4.3Tests
4.3.1DUT setup and environmental conditions
For tests requiring continuous operation of the DUT, the DUT is placed in a test bed that canbe adjusted to the prescribed temperature and humidity to conditions.The test conditions aremonitored to verify that no abnormalities occur when the chamber environment reaches theprescribed conditions.For tests that do not require continuous operations of the DUT, theDUT may be placed in the test bed and the test bed may be deposited in the chamber, but thetest bed need not be put in the chamber. When depositing and removing the DUT and testbed for either test, the operator shall ensure that:
– water does not drip onto the DUT;
– the DUT is not directly immersed in water.
4.4Post-treatment
After completion of the tests, first the application of mechanical stress and strain, or vibration,is halted, and then the DUT is removed from the chamber and returned to standard conditions.However,this shall not apply to cases in which the DUT clearly recovers from its degradedstate after the application of mechanical stress and strain, or vibration, is halted at the testingtemperature because a correct result is not possible.
4.5 Final measurements
The methods of measurement used in moist heat tests shall conform to the methods set forthin lEC 62047-30. The degraded state of a DUT is evaluated by comparing the finalmeasurements to the initial measurements.The environmental conditions for measurementsshall include:
– ambient temperature: 25C± 3°c;
– relative humidity: 45 % to 75 %;
– atmospheric pressure: 86 kPa to 106 kPa.
As a general rule, final measurements shall be conducted within 48 h from the completion oftests after verifying that the surface of the DUT is dry. When conducting intermediatemeasurements prior to the final measurements,the DUT’shall be deposited back into thetesting chamber within 96 h after being removed for measurements. Final measurements arepreferably completed within 96 h after halting voltage application to the DUT.
The chamber shall be capable of maintaining its entire interior at the set temperature ±2 °cand the set humidity ±5 % during the test.The applied mechanical stress and strain, and theoperating method shall be established with consideration for the limits of the DUT. Theapplication circuit shall be considered to account for load conditions and other factors in orderthat the operating state of the DUT be suitably maintained.
NOTE 1 The degree of degradation in a device under test (DUT) is evaluated by measuring the piezoelectricproperties of the DUT before and after applying the environmental stress of temperature and humidity.
NOTE 2 The degree of degradation in a DUT is evaluated using the measurement methods in IEC 62047-30.
NOTE 3 A test circuit for testing a plurality of DUT simultaneously is designed so that failure of one DUT during atest does not affect the other DUT.

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