IEEE 1450.6.1:2009 pdf free download – IEEE Standard for Describing On-Chip Scan Compression
The test logic insertion stage has the best understanding of the test structure being implemented. Test logicinsertion tools are developed based on specific compression structures and have many special design rulechecks implemented so customers have as good a chance as possible to generate working, highly effectivepatterns the first time. The time and knowledge necessary to develop all of the design rule checks issignificant. Due to this, the OCl flow presumes the pattern generation tool does not need to perform teststructure verification. In the case where a design house is integrating a core with in-house design logic, thetest structure in the core is presumed to be verified by the core provider and all core-level OCI informationneeded for pattern generation shall be in the OCI-compliant CTL file the core provider gives the designhouse. The design house integrating the core is responsible for generating and verifying the final OCIinformation passed to pattern generation.
The OCI-specific information passed from test logic insertion to pattern generation includes patternsequence restrictions, a description of compression hardware,netlist mapping points,and vendor-specificdata to ensure vendor flows are as easy to use as possible when using OCl. For a more detailed descriptionof how CTL is leveraged to pass information from test logic insertion to pattern generation, see 1.4.
The pattern generation stage can be very time consuming.The automatic test pattern generator (ATPG)determines which logic values are needed on scan cells to detect the most faults by each test pattern. After apattern is generated, it is then simulated to determine how many faulty locations have been detected.This sequence is repeated until as many as possible faulty locations have been detected.For chips without on-chip scan compression, the value loaded and unloaded from each scan cell can be mapped directly to aunique value loaded into the chip and to a unique value unloaded from the chip. Only sequence definitionsthat describe how to initialize, load, unload, and apply tests are needed by pattern generation for this case.
On-chip scan compression needs more information.Putting a logic value in a scan cell requires a value to beloaded into the chip at a previous point in time and likely forces other scan cells to be put to certain logicvalues. Checking that a value is in a scan cell may require values in masking logic or on other scan cells.Also, on-chip scan compression hardware may restrict the length of a sequence or require a relationshipbetween sequences because of how the hardware is implemented. To do pattern generation efficiently, OCIpasses pattern generation sequences,sequence limitations/relationships, and symbolic descriptions of thecompression hardware created by the test logic insertion stage.
The output test patterns generated by pattern generation need to be diagnosable using both EDA diagnosis,that can isolate to a gate or net, and on the tester, where isolation is possible due to the failing scan cell orscan chain. To enable this capability, the pattern generation stage shall identify key events in the pattern dataand pass this information to diagnosis. The information is passed through OCl by updating the sequencesand/or by adding information to the test pattern data. For a more detailed description of how CTL isleveraged to pass information from pattern generation to diagnosis, see 1.4.
The diagnosis stage uses the key event information added by pattern generation to map each automatic testequipment (ATE) failure back to a list of defect candidates that might have caused that failure. Thediagnosis stage does not add any new information to the OCI file.