IEEE 1838:2019 pdf free download – IEEE Standard for Test Access Architecture for Three-DimensionalStacked lntegrated Circuits
1.2 Three-dimensional integrated circuits (ICs) stacking technology
The market continues to pull for integrated circuits (ICs) with higher performance, better energy-efficiency,and lower cost. While conventional transistor scaling runs into increasing technical and financial hurdles,the baton in the race to create attractive new IC products that meet market expectations is gradually beingtaken over by innovations in multi-die stack-assembly and packaging techniques. Large-array fine-pitchmicro-bumps implement dense high-performance low-power inter-die interconnects. Through-silicon viasin combination with wafer thinning provide electrical connections via the back-side of a die’s substrate,enabling stacks of more than two dies.Interposer dies, possibly implemented in a passive technology, offerlow-cost high-performance ways to interconnect multiple dies. Packaging costs can be drastically reduced byusing cheaper materials and processes and by turning packaging into a wafer-level operation.The UO-to-pinfan-out functionality of package substrates can be replaced by redistribution metal layers, cost-effectivelymanufactured at wafer level.And the cost of plastic or ceramic packages can be circumvented by applyingepoxy mold compounds at wafer level.
These and other interconnect, assembly, and packaging technology innovations have led to a wide range ofmulti-die stack architectures, including so-called “2.5D”-stacked lCs (SICs) consisting of multiple active diesstacked side-by-side on a passive silicon interposer base,”3D”-SICs comprising a tower of stacked activedies, and multi-tower-SICs that consist of multiple towers of stacked active dies side-by-side on a passivesilicon interposer.
Like all micro-elcctronic products, these die stacks need to be tested before they can be shipped with acceptablequality levels to their customers. We distinguish the following tests: (1) pre-bond tests prior to stacking,(2)mid-bond tests on incomplete, partial stacks,(3) post-bond tests on complete yet not packaged stacks, and (4)final tests on the final packaged product.The number of possible test flows grows quickly with the number ofdies in the stack and hence is subject of automated trade-off evaluation and optimization (see,[B1],[B4], and[B8]).
1.3 Motivation for a 3D-DfT standard
A well-architected DfT access infrastructure is indispensable for achieving a high-quality test. Not onlydo we need conventional 2D-DfT structures (such as internal scan chains,test data compression circuitry,IEEE Std 1500 wrappers around embedded cores, andor built-in self-test (BIST) engines) that provide testaccess within a single die, we also need new approaches for testing stacked systems. Especially once a (partialor complete) vertical stack has been formed (i.e., in mid-bond, post-bond, or final testing phases), we also neednovel3D-DfT structures that provide test access from (and to) the external stack I/Os to (and from) the variousdies and inter-die interconnects.For example: if a stack consists of three dies and test access from external testequipment is exclusively possible via the stack IOs that are concentrated in, say, Die 1, then Die 1 and Die 2need to cooperate in transporting test stimuli and responses up and down the stack in order to be able to testDie 3.
To enable separation of the test development as well as test execution for the various dies in the stack, the3D-DfT architecture should enable modular testing,i.e., tests for dies and interconnect layers between adjacentstacked dies can be developed and executed individually.Several ad-hoc 3D-DfT architectures have beenproposed, among others based on IEEE. Std 1149.1,IEEE Std 1500, and IEEE Std 1687.These architectures allhave their specific strong and weak points. However, these ad-hoc 3D-DfT architectures do not inter-operatetogether.Hence, there is a need for a per-die 3D-DfT standard, such that if compliant dies (even if designedand developed by different teams or different companies) are brought together in a die stack, a basic minimumof test features should work across the stack.This is exactly the aim of IEEE Std 1838.